Photolithography is one of the most frequently employed semiconductor wafer processing techniques used to manufacturer integrated circuits (IC's). Photolithography comprises a process for forming a pattern (i.e., via photographic transfer) of complex circuit diagrams onto a semiconductor wafer surface for etching. These patterns are defined on the wafer in a succession of exposure and processing steps to form a number of superimposed layers. Manufacturing processes for IC devices depend upon extremely accurate reproduction of these patterns onto the wafer surface.
During each photolithographic step, deviations are commonly introduced that distort the photomask image being transferred onto a wafer surface. These deviations depend on the characteristics of a pattern being transferred, topology of the wafer, and a variety of other processing parameters. Processing deviations adversely affect the performance of a semiconductor device. Deviations that affect dimensions and shapes of wafer features caused by light intensity in a particular vicinity of a wafer effecting the light intensity in neighboring vicinities are referred to as optical proximity effects. Various compensation methods for optical proximity effects have been developed in efforts to improve the image transfer process. One method known to those skilled at the art is optical proximity correction (OPC). OPC consists of selectively biasing mask patterns to compensate for a proximity effect that occurs in an optical image transfer process.
An example of an OPC process involves identifying gate regions in a design where shapes at these regions are sorted according to their geometric types. These design shapes share at least one side with a second design shape. Grouping of sorted design shapes is performed according to their widths. Grouped design shapes identified as gate regions are then biased based on the applicable OPC. Commercial OPC software is available and used to obtain a corrected pattern through theoretical image correction on plain wafers. However, this software is not effective for wafer topography correction or other process-induced critical dimension (CD) variations.
Additional problems that cause optical proximity effects on the surface of a wafer are the topography of the wafer surface formed after the deposition of a polysilicon and an anti-reflectance coating layer. As device sizes shrink, the wavelength of light used in photolithography is decreased and numerical apertures of lenses are increased, leading to a reduced depth of focus. The depth of focus represents the relationship of a wafer surface being exposed to a stepper. Most of the depth of focus available is consumed by topography variations for non-planar substrates. Topography variations exist even after a planarization process, such as chemical mechanical polishing (CMP), has been performed to flatten a wafer surface. Lack of planarity on the overlying surfaces can degrade the semiconductor device quality making the depth of focus a critical processing parameter. If the surface is not planar, it is impossible to have the whole surface exposed while in proper focus. Therefore, a trade-off between the maximum achievable resolution and the usable depth of focus in a photolithographic process has to be made. The usable depth of focus determines the overall performance of the photolithographic process. In the case where an image needs to be reproduced on a given topography, the usable depth of focus can be a more significant factor than the achievable resolution. Thus, there exists a need in the art for a 3D OPC model method that links a deterministically predicted topography map (pattern density) to a measured CD (i.e., scale) in the photolithographic process to overcome these limitations.